The present invention relates to a data processor, or more particularly, to a technology effectively utilized for, for example, a central processing unit (CPU), or a microcomputer or data processor including the CPU.
A microcomputer realized with semiconductor integrated circuits has undergone extension of an address space, expansion of an instruction set, or an increase in a processing speed. For example, Japanese Unexamined Patent Publication No. Hei5(1993)-241826 or No. Hei6(1994)-51981 describes an example of a microcomputer that has the address space thereof extended or the instruction set thereof expanded while maintaining the interchangeability on an object level.
Moreover, Japanese Unexamined Patent Publication No. Hei8(1996)-263290 describes an example of a microcomputer whose CPU is interchangeable with a CPU that executes basic instructions in two execution states, and whose processing is so fast as to execute the basic instructions while bringing them into one state. Furthermore, the microcomputer enjoys really fast processing owing to incorporation of a multiplier independent of the CPU.
Owing to the realization of fast processing, equipment to be controlled by a microcomputer can be designed to operate fast or can be sophisticated. Otherwise, a microcomputer that conventionally consists of a plurality of semiconductor integrated circuits can be designed compactly by integrating the semiconductor integrated circuits with one another.
The present inventor has made the proposal described below in the previous application (Japanese Unexamined Patent Publication No. 2000-357089). Namely, the width of an internal data bus is made larger than at least a basic unit of an instruction (for example, a word). An instruction register is included for holding a plurality of units of a read instruction. A means is included for monitoring the number of bits representing an instruction present in the instruction register. Based on a basic unit execution time (during which one execution state persists), an instruction is executed so that the instruction will be read in one execution state and a program counter (PC) will be incremented at the same time, and the instruction will have an effective address thereof calculated or undergo a data operation in another execution state. An execution state in which the instruction is merely read can therefore be omitted. In response to a direction given by the monitoring means, the execution state in which the instruction is merely read is omitted (skipped) depending on the number of bits representing the instruction present in the instruction register. Consequently, the number of bits to be read as an instruction during instruction execution is increased or decreased based on the instruction length. Thus, it is intended to reduce the number of execution states and achieve fast processing.